In the semiconductor production industry, various processing steps are used to fabricate integrated circuits on a semiconductor wafer. These steps include deposition of a conducting layer on the silicon wafer substrate; formation of a photoresist or other mask such as titanium oxide or silicon oxide, in the form of the desired metal interconnection pattern, using standard lithographic or photolithographic techniques; subjecting the wafer substrate to a dry etching process to remove the conducting layer from the areas not covered by the mask, thereby etching the conducting layer in the form of the masked pattern on the substrate; removing or stripping the mask layer from the substrate typically using reactive plasma and chlorine gas, thereby exposing the top surface of the conductive interconnect layer; and cooling and drying the wafer substrate by applying water and nitrogen gas to the wafer substrate.
Ion implantation is another processing step commonly used in the fabrication of the integrated circuits on the wafer. Ion implantation is a form of doping, in which a substance is embedded into the crystal structure of the semiconductor substrate to modify the electronic properties of the substrate. Ion implantation is a physical process which involves driving high-energy ions into the substrate using a high-voltage ion bombardment. The process usually follows the photolithography step in the fabrication of the circuits on the wafer.
The ion implantation process is carried out in an ion implanter, which generates positively-charged dopant ions in a source material. A mass analyzer separates the ions from the source material to form a beam of the dopant ions, which is accelerated to a high velocity by a voltage field. The kinetic energy attained by the accelerated ions enables the ions to collide with and become embedded in the silicon crystal structure of the substrate. Finally, the doped silicon substrate is subjected to a thermal anneal step to activate the dopant ions.
The thermal anneal step is typically carried out in a single-wafer rapid thermal processing (RTP) chamber as nitrogen and argon or helium is distributed into the chamber. In the RTP chamber, the wafer is subjected to rapid heating (up to about 150 degrees C. per second) to a target temperature of up to about 1000 degrees C., with a short dwell time. The rapid heating of the wafer anneals the wafer and restores lattice damage and electrically activates the implanted dopant ions. Furthermore, rapid thermal processing is commonly used to facilitate optimum junction depth control in shallow implants.
In advanced lamp RTP anneal processes (particularly spike anneal processes), backside helium is used to cool the wafer after annealing. However, the use of backside helium to cool the wafer is incapable of facilitating the rapid cooling needed for the latest advances in semiconductor technology, since slow cooling results in the short channel effect. Furthermore, the cooling uniformity of backside helium is poor. Accordingly, a new and improved rapid cooling system is needed for the rapid cooling of wafers after a rapid thermal processing (RTP) step, particularly after shallow junction anneal processes.